This invention relates to nonvolatile memory in integrated circuits. More specifically, the invention relates to Electrically Erasable Programmable Read Only Memory (EEPROM) semiconductor architectures.
Nonvolatile memory has the advantage of being able to store data in the absence of a power supply. This property is useful for applications such as the storage of inputs used for control functions or program settings. Nonvolatile memory cells are of two general forms: electrically programmable read-only memory (EPROM) and electrically erasable and programmable read-only memory (EEPROM). Typically, these devices use two transistors to form an electrically isolated floating gate element which can store electrons in varying amounts. Conventional EEPROM architectures are shown in U.S. Pat. No. 5,465,231 to Ohsaki, xe2x80x9cEEPROM and Logic LSI Chip Including Such EEPROMxe2x80x9d issued Nov. 7, 1995; and U.S. Pat. No. 6,100,560 to Lovett, xe2x80x9cNonvolatile Cellxe2x80x9d issued Aug. 8, 2000, the disclosures of which are incorporated herein by reference.
The EEPROM cells described in the above-referenced patents consist of a memory transistor having a floating gate that is capacitively coupled to a select gate. A thin oxide layer is typically used to insulate the floating gate from the drain of the memory transistor. The floating gate stores electrical charge in response to a voltage applied across the source and drain of the memory transistor and a second voltage applied across the source and drain of a second transistor. The floating gate can then be thought of as having two states: a xe2x80x9cprogrammedxe2x80x9d state (charged above a set level) and xe2x80x9cunprogrammedxe2x80x9d state (charged below the set level). Thus the floating gate functions can store binary information when floating gate charge is applied in the above manner as the charged state can represent a first binary state and the uncharged may be used to represent a second binary state.
The typical EEPROM is generally programmed and erased by charging or discharging the floating gate by applying appropriate voltages to the control gates and the substrate. The process is accomplished by using electron tunneling from an auxiliary conductor by use of the Fowler-Nordheim electron-tunneling mechanism (FN tunneling). FN tunneling is the quantum mechanical effect that allows electrons to pass through an energy barrier at the poly/oxide barrier. To allow for FN tunneling, the oxide layer in the first transistor is typically of a thickness of 100 Angstroms or less.
The programming function is performed by charging the floating gate with electrons. A relatively high electric potential is applied to the control gate of the selected memory cell transistor. This is sensed by the data read lines as a logical one or zero. The floating gate is then charged according to the FN tunneling effect. The accumulation of electrons at the floating gate increases the threshold voltage of the memory cell transistor. The EEPROM memory cell is erased by discharging the floating gate. A relatively high electrical potential with respect to the control gate is applied to the substrate and the floating gate discharges via FN tunneling. Data can thus be written into a selected memory cell transistor by performing either a program operation or an erase operation.
A disadvantage with current EEPROM technology is that it is generally not compatible with the standard complementary metal oxide semiconductor (CMOS) process. The typical EEPROM memory cell is shown in FIG. 1 and is generally indicated at reference numeral 10. The cell 10 consists of a stacked gate structure in which a floating gate (F.G.) 11 and a control gate (C.G.) 12 are stacked upon a singe transistor 13 by depositing a gate oxide layer 14 and the polycrystalline silicon (i.e., xe2x80x9cpolysiliconxe2x80x9d or simply xe2x80x9cpolyxe2x80x9d) layer 11, followed by a second thin oxide 15 and poly layer 12, as in FIG. #1. Poly 1 is typically referred to as the floating gate 11, and poly 2 as the control gate 12. A metalization layer 17 penetrates the oxide layer 15 and controls the control gate 12. This prior art cell is suitable for high density memory applications, but is not generally compatible with standard CMOS technology. The standard CMOS process entails a one-layer polysilicon deposition step while the typical EEPROM cell requires two polysilicon deposition steps to form the floating gate 11 and control gate 12 as well as a step for the deposition of a thin oxide layer 14 between the two polysilicon layers 11, 12. These additional process steps are not appropriate for non-memory applications, and add to the expense in production of the cells. An example of a non-memory application is an analog circuit requiring only a small number of bits for trimming or device configuration. U.S. Pat. No. 5,930,613 to Schlais et al. describes an EPROM cell having a large lateral capacitor manufactured in accordance with standard CMOS processes. However, the architecture shown therein is not applicable to an EEPROM cell. Thus there is a need for an EEPROM functionally equivalent to the conventional stacked gate type EEPROM that can be formed through the standard CMOS process.
The object of this invention is to address the drawbacks of the current art and provide a nonvolatile memory cell that is produced with fewer process steps and thus more economically. Further object and advantages of the invention will become apparent from a consideration of the drawings and ensuing descriptions.
The present invention is an EEPROM cell having a unique configuration. The cell is comprised of a standard NMOS or PMOS type transistor connected to a Metal-Insulator-Metal (MIM), or Poly-Insulator-Poly (PIP) capacitor. The two devices form a floating gate between the gate of the first transistor and one terminal of the MIM or PIP capacitor. The floating gate stores electrical charge via Fowler-Nordheim tunneling (FN tunneling) in response to a voltage applied to the second terminal of the capacitor. The floating gate functions as a memory cell when floating gate charge is applied in the above manner. The capacitor may be deposited in a single layer of oxide by interlacing anode/cathode fingers of the capacitor in a horizontal plane with the oxide forming the dielectric between the fingers. Alternately, the capacitor may be formed by interconnecting the multiple fingers in multiple vertical layers.